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as1376 1a, low input voltage, low quiescent current ldo www.austriamicrosystems.com/lods/as1376 revision 1.4 1 - 19 datasheet 1 general description the as1376 is a dual supply rail linear regulator designed to deliver 1a of load current while consuming only 67a (typ) of ground current. in the typical post regulation application v bias is directly connected to the main input supply, (range 2.5v...5.5v) and v in is supplied by the output voltage of a host dc-dc converter (range 0.7v...4.5v). the device offers excellent dropout (120mv @ 1a) and transient perfo rmance. in shutdown (enable pin pulled low), the device turns off and reduces qui escent current consumption to 10na (typ) at both v bias and v in terminals. in shutdown, a 100 ? (typ) discharge path is connected between out put and ground to provide rapid discharge of the overall load capacitance connected to the as1376 output terminal. auto- discharge minimizes the possibility that v out > v in during shutdown. when v out > v in , reverse current flows through the inherent body diode of the n-channel series pass transistor. the as1376 also features internal protection against over- tem perature, over-current and under-voltage conditions. the device is available in an 8-pin 2x2 tdfn package and is qua lified for operation over the -40oc to +85oc temperature range. the device is available in fixed output voltages from 0.5v up to 2.2v in 1 00mv steps (50mv from 0.5v to 1.1v). see ordering information on page 18 . figure 1. as1376 - typical application diagram 2 key features ?? ultra-low dropout voltage: <120mv @ 1a load ?? output voltages: 0.5v to 2.2v ?? input voltage: 0.7v to 3.6v ?? bias supply voltage: 2.5v to 5.5v ?? maximum output current: 1a ?? output voltage accuracy: 2% ?? low shutdown current: 20na ?? wide band v bias psrr 45db (typ) 10ma load ?? integrated overtemperature / overcurrent protection ?? chip enable input ?? minimal external components required ?? operating temperature range: -40c to +85c ?? 8-pin 2x2mm tdfn package ?? 2 weeks availability for non-standard devices between 0.5v and 1.1v in 50mv steps and between 1.1v and 2.2v in 100mv steps. 3 applications the devices are ideal for powering cordless and mobile phones, mp3 players, cd and dvd players, pdas, hand-held computers, digital cameras and any other hand-held and/or battery-powered device. ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 2 - 19 as1376 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin number pin name description 1, 2 vin un regulated input voltage . 0.7v to 3.6v. bypass this pin with a capacitor to gnd. 3 vbias bi as input voltage. 2.5v to 5.5v. bypass this pin with a capacitor to gnd. 4 gnd ground. 5 en enable. pull this pin to low to disable the device. 6 nc lea ve this pin unconnected. 7 fb feed back pin. connect to vout to select the factory-preset output voltage. for the adjustable version connect to an external resistor divider to set output voltage. 8 vout regulated output v oltage . 0.5v to 3.3v. bypass this pin with a capacitor to gnd. 9 exposed pad . this pad is not connected internally. ensure a good connection to the pcb to achieve optimal thermal performance. 5 en 3 vbias 2 vin 1 vin 8 vout as1376 4 gnd 7fb 6nc 9 ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 3 - 19 as1376 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units notes electrical parameters vin to gnd -0.3 5 v vbias , en to gnd -0.3 +6.5 v vout to gnd -0.3 v in + 0.3 v output short-circuit duration indefinite input current (latch-up immunity) -100 100 ma jedec 78 electrostatic discharge electrostatic discharge hbm 2 kv norm: mil 883 e method 3015 temperature ranges and storage conditions thermal resistance ? ja 97 oc/w junction-to-ambient thermal resistance is very dependent on application and board-layout. in situations where high maximum power dissipation exists, special attention must be paid to thermal dissipation during board design. junction temperature +125 oc storage temperature range -55 +150 oc humidity non-condensing 5 85 % package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 4 - 19 as1376 datasheet - electrical characteristics 6 electrical characteristics v in = v out + 0.2v, v bias = v out + 1.5v (or 2.5v whichever is larger), en = v bias , c in = c out = 1f, c bias = 4.7f, t amb = -40oc to +85oc. typical values are at t amb = +25oc (unless otherwise specified). table 3. electrical characteristics symbol parameter conditions min typ max units t amb operating temperature range -40 +85 c v in input voltage 0.7 3.6 v v bias bias supply voltage 2.5 5.5 v v out output voltage available in 100mv steps (see ordering information on page 18) 0.5 3.3 v v out(nom) - v out output voltage accuracy i out = 100a -1.5 +1.5 % i out = 0a to 1a -2 +2 v fb feedback voltage 1 i out = 100a 492 500 508 mv i out = 0a to 1a 490 500 510 ? v out / ? v in line regulation v in i out = 100a 40 v/v ? v out / ? v bias line regulation v bias i out = 100a 135 v/v ? v ldr load regulation i out = 1ma to 1a 0.0002 %/ma i out output current 2 1a i lim current limit v out forced to 90% of nominal v out 1.35 a v drop -v in output voltage dropout v in v bias = v out + 1.5v, i out = 1a 120 mv v bias = v out + 1.8v, i out = 1a 115 v bias = v out + 2.1v, i out = 1a 110 mv v bias = 5.5v, i out = 1a 105 v drop - v bias output voltage dropout v bias i out = 500ma 0.85 v i out = 1a 1.1 en output voltage noise f = 10hz to 100khz, i out = 1ma 65 v rms psrr - v in power-supply rejection ratio sine modulated v in f = 100hz, i out = 10ma 78 db f = 1khz, i out = 10ma 61 f = 10khz, i out = 10ma 54 f = 100khz, i out = 10ma 60 psrr - v bias power-supply rejection ratio sine modulated v bias f = 100hz, i out = 10ma 69 db f = 1khz, i out = 10ma 51 f = 10khz, i out = 10ma 45 f = 100khz, i out = 10ma 45 i q_vbias quiescent current into v bias 60 120 a i q_vin quiescent current into v in i out = 0ma 6.5 8 i shdn - v bias shutdown current into v bias v en = 0v 0.02 a i shdn - v in shutdown current into v in 0.02 ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 5 - 19 as1376 datasheet - electrical characteristics note: all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical qual ity control) methods. shutdown i en enable input bias current 0.001 1 a v ih enable input threshold v in = 0.7 to 3.6v 1 v v il 0.4 thermal protection t shdn thermal shutdown temperature 155 oc ? t shdn thermal shutdown hysteresis 30 oc transient characteristics ? v out dynamic load transient response v bias 35 mv t on exit delay from shutdown settling to 95%, no load 72 s c out output capacitor load capacitor range 1 10 f maximum esr load 500 m ? 1. valid for adjustable output version only. 2. limit guaranteed by design and characterization. table 3. electrical characteristics symbol parameter conditions min typ max units ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 6 - 19 as1376 datasheet - typical operating characteristics 7 typical operating characteristics v in = 1.2v, v bias = 2.5v, v out = 1.0v, en = v bias , c in = c out = 1f, c bias = 4f. typical values are at t amb = +25oc (unless otherwise specified). figure 3. bias supply current vs. bias supply voltage figure 4. bias supply current vs. bias supply voltage 50 55 60 65 70 2.533.544.555.5 bias supply voltage (v) bias supply current (a) no lo ad io ut = 70 0 ma io ut = 1a 40 45 50 55 60 65 70 75 80 2.5 3 3.5 4 4.5 5 5.5 bias supply voltage (v) bias supply current (a) - 40c + 25c + 90c figure 5. ground current vs. bias supply voltage figure 6. ground current vs. bias supply voltage 50 55 60 65 70 75 80 85 90 2.5 3 3.5 4 4.5 5 5.5 bias supply voltage (v) ground current (a) - 40c + 25c + 90c no lo ad 50 55 60 65 70 75 80 85 90 95 2.533.544.555.5 bias supply voltage (v) ground current (a) - 40c + 25c + 90c io ut =1a figure 7. ground current vs. bias supply voltage figure 8. ground current vs. load current 60 65 70 75 80 2.5 3 3.5 4 4.5 5 5.5 bias supply voltage (v) ground current (a) no l oad i out = 1a 50 55 60 65 70 75 80 85 0 100 200 300 400 500 600 700 800 900 1000 load current (ma) ground current (a) -40c +2 5c +9 0 c ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 7 - 19 as1376 datasheet - typical operating characteristics figure 9. psrr v in ; v in =1.5v dc + 300mv pk figure 10. psrr vbias; v bias =3.5v dc + 500mv pk -100 -90 -80 -70 -60 -50 -40 100 1000 10000 100000 frequency (hz) input voltage - psrr (db) -100 -90 -80 -70 -60 -50 -40 100 1000 10000 100000 frequency (hz) bias supply voltage - psrr (db) io ut =10ma figure 11. line regulation: v out vs. v in ; i out =100 a figure 12. line regulation: v out vs. v in ; v bias =5.5v 0.985 0.99 0.995 1 1.005 1.01 1.015 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 input voltage (v) output voltage (v) 0.985 0.99 0.995 1 1.005 1.01 1.015 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 input voltage (v) output voltage (v) figure 13. load regulation: v out vs. i out figure 14. output voltage vs. temperature; i out =1ma 0.985 0.99 0.995 1 1.005 1.01 1.015 0 200 400 600 800 1000 output current (ma) output voltage (v) 0.985 0.99 0.995 1 1.005 1.01 1.015 -40 -20 0 20 40 60 80 temperature (c) output voltage (v) ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 8 - 19 as1376 datasheet - typical operating characteristics figure 15. dropout v in vs. temperature; i out =1a figure 16. enable start-up 50 75 100 125 150 175 200 -40-200 20406080 temperature (c) dropout v in (mv) 50s/div 500mv/div 500mv/div en v out ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 9 - 19 as1376 datasheet - detailed description 8 detailed description the as1376 is a low-dropout, low-quiescent-current linear regulator intended for ldo regulator applications where output curren t load requirements range from no load to 1a. all devices come with fixed output voltage from 0.5v to 3.3v. (see ordering information on page 18) . shutdown current for the whole regulator is typically 20na. the de vic e has integrated short-circuit and over current protection . under-voltage lockout prevents erratic operation when the input voltage is slowly decaying (e.g. in a battery powered application). thermal p rotection shuts down the device when die temperature reaches 150c. this is a useful protection when the device is under sustained short circui t conditions. as illustrated in figure 17 , the devices comprise voltage reference, error amplifier, n-channel mosfet pass transistor, internal voltage divider, current limiter, thermal sensor and shutdown logic. the bandgap reference is connected to the inverting input of the error amplifier. the error amplifier compares this reference w ith the feedback voltage and amplifies the difference. if the feedback voltage is lower than the reference voltage, the n-channel mosfet gate is pulled higher, allowing more current to pass to the output, and increases the output voltage. if the feedback voltage is too high, the pass-tr ansistor gate is pulled down, allowing less current to pass to the output. when the adjustable output variant is selected, an external resistor voltage divider is connected to fb pin and a sample of the ou tput is compared to the 500mv reference. when a fixed output variant is chosen, fb must be connected to the output pin. depending upon the variant chosen, the internal refe rence is trimmed to the final output voltage. see electrical characteristics (page 4) for final voltages and tolerances. figure 17. as1376 block diagram r discharge shutdown power on control logic reference core thermal overload protection bandgap voltage & current reference + - error amplifier q discharge out vbias vin gnd q power as1376 en ep fb vin ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 10 - 19 as1376 datasheet - detailed description 8.1 output voltages standard products are factory-set with output voltages from 0.5v to 2.2v. a two-digit suffix of the part number identifies the nominal output (see ordering information on page 18) . non-standard devices are available. for more information contact: http://www.austriamicrosystems.com/contact 8.2 advantages of dual suppl y architecture vs t raditional single supply approach compared to the traditional single supply approach, employing a p-channel series pass mosfet, the dual rail architecture ensure s improved performances in a ldo when operating at very low input voltages below the threshold of the internal series power n-channel mosf et. the extra supply voltage at v bias (v bias > v in ) ensures that the n-channel mosfet always operates above its threshold voltage. figure 18 shows simplified block diagrams of single supply p-channel ldo and dual rail n-channel series pass architectures. figure 18. single vs. dual supply the p-channel ldo uses a pmos output transistor connected in a c ommon source configuration. during regulation, the p-channel ga te-source voltage moves between v in and gnd as the load demands. the dual supply approach is based on an n-channel output transistor in common drain configuration where the source is connected to the regulated output. during regulation, the n-channel gate source voltage increases from v out to v bias as the load demands. as the drain voltage is not shared with the remaining blocks of the circuit, its value can be chosen independently. the n-channel source follower design allows improved efficiency and dropout at low input voltages and provides f aster load transient response. bandgap error amplifier pmos + - core blocks v in bandgap error amplifier nmos + - core blocks v in v bias v out v out single supply dual supply ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 11 - 19 as1376 datasheet - application information 9 application information 9.1 dropout voltage dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. at this point, the outp ut voltage change follows the input voltage change. dropout voltage may be measured at different currents and, in particular at the regulator max imum one. from this is obtained the mosfet maximum series resistance over temperature etc. more generally: (eq 1) dropout is probably the most important specification when the regulator is used in a battery application. the dropout performan ce of the regulator defines the useful ?end of life? of the battery before replacement or re-charge is required. figure 19. graphical representation of dropout voltage figure 19 shows the variation of v out as v in is varied for a certain load current. the practical value of dropout is the differential voltage (v out - v in ) measured at the point where the ldo output voltage has fallen by 100mv below the nominal, fully regulated output value. the n ominal regulated output voltage of the ldo is that obtained when there is 500mv (or greater) input-output voltage differential. 9.2 auto-discharge as1376 features an auto-discharge function that discharges the load capacitance through a 100 ? (typ) path to ground when the device is pl aced in shutdown. this helps to minimizes the possibility that v out > v in during shutdown caused by differing capacitance discharge rates at v in and v out terminals. when v out > v in , reverse current flows through the inherent body diode of the n- channel series pass transistor. this current should be limited to 50ma or less. if this is not possible, then an external schottky diode should be connected between v out (anode) and v in (cathode) to bypass the discharge current around the as1376. 9.3 efficiency low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the re gulator efficiency is directly related to quiescent current and dropout voltage. efficiency is given by: efficiency = %( e q 2 ) where: ? i q = quiescent current of ldo measured at v bias v dropout i load r series ? = dropout voltage 100mv v in v out v out v in v out v in =v out(typ) +0.5v v in v load i load ? v in i q i load + ?? -------------------------------------- - 100 ? ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 12 - 19 as1376 datasheet - application information 9.4 power dissipation maximum power dissipation (pd) of the ldo is the sum of the power dissipated by the internal series mosfet and the quiescent cu rrent required to bias the internal voltage reference and the internal error amplifier, and is calculated as: watts (eq 3) internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calcul ated as: watts (eq 4) total ldo power dissipation is calculated as: watts (eq 5) 9.5 junction temperature under all operating conditions, the maximum junction temperature should not be allowed to exceed 125oc (unless the data sheet s pecifically allows). limiting the maximum junction temperature requires knowledge of the heat path from junction to case ( ? jc oc/w fixed by the ic manufacturer), and adjustment of the case to ambient heat path ( ? ca oc/w) by manipulation of the pcb copper area adjacent to the ic position. figure 20. package physical arrangements fig ure 21. steady state heat flow equivalent circuit pd max ?? seriespass ?? i load max ?? = v in max ?? v out min ?? ? ?? pd max ?? bias ?? v in max ?? i q = pd max ?? total ?? pd max ?? seriespass ?? pd max ?? + bias ?? = chip pcb package transfer layer cs-wlp package solder balls junction t j c package t c c pcb/heatsink t s c ambient t a c chip power r ? jc r ? cs r ? sa ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 13 - 19 as1376 datasheet - application information total thermal path resistance: (eq 6) junction temperature (t j oc) is determined by: oc (eq 7) 9.6 explanation of st eady state specifications 9.6.1 line regulation line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. it is a measure of the regulator?s ability to maintain a constant output voltage when the input voltage changes. line regulation is a measure of the d c open loop gain of the error amplifier. more generally: line regulation = and is a pure number (eq 8) in practise, line regulation is referred to the regulator output voltage in terms of % / v out . this is particularly useful when the same regulator is available with numerous output voltage trim options. line regulation = % / v (eq 9) 9.6.2 load regulation load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. it is a measure of the regulator?s ability to maintain a constant output voltage when the load changes. load regulation is a measure of the dc closed loop output resistance of the regulator. more generally: load regulation = and is units of ohms ( ? )( e q 1 0 ) in practise, load regulation is referred to the regulator output voltage in terms of % / ma. this is particularly useful when t he same regulator is available with numerous output voltage trim options. load regulation = % / ma (eq 11) 9.6.3 setting accuracy accuracy of the final output voltage is determined by the accuracy of the ratio of r1 and r2, the reference accuracy and the in put offset voltage of the error amplifier. when the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification. when the regulator has a set terminal, the output voltage may be a djusted externally. in this ca se, the tolerance of the external resistor network must be incorporated into the final accuracy calculation. generally: (eq 12) the reference tolerance is given both at 25oc and over the full operating temperature range. 9.6.4 total accuracy away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. generally: total % accuracy = setting % accuracy + load regulation % + line regulation % (eq 13) r ? ja r ? jc r ? cs r ? sa ++ = t j pd max ?? r ? ja ? ?? t amb + = ? v out ? v in ---------------- ? v out ? v in ---------------- 100 v out ------------ ? ? v out ? i out ---------------- ? v out ? i out ---------------- 100 ? v out ---------------- ? v out v set ? v set ? ?? r 1 ? r 1 ? r 2 ? r 2 ? ?? ?? ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 14 - 19 as1376 datasheet - application information 9.7 explanation of dynamic specifications 9.7.1 power supply rejection ratio (psrr) known also as ripple rejection, this specification measures the ability of the regulator to reject noise and ripple beyond dc. psrr is a summation of the individual rejections of the error amplifier, reference and ac leakage through the series pass transistor. the specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the desig ner in low quiescent current conditions. generally: pssr = db using lower case to indicate ac values (eq 14) power supply rejection ratio is fixed by the internal design of the regulator. additional rejection must be provided externally . 9.7.2 output capacitor esr the series regulator is a negative feedback amplifier, and as such is conditionally stable. the esr of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. excessive esr values may a ctually cause instability by excessive changes to the closed loop unity gain frequency crossover point. the range of esr values for stability is usually shown either by a plot of stable esr versus load current, or a limit statement in the datasheet. some ceramic capacitors exhibit large capacitance and esr variations with temperature and dc bias. z5u and y5v capacitors may b e requ ired to ensure stability at temperatures below t amb = -10oc. with x7r or x5r capacitors, a 1f capacitor should be sufficient at all operating temperatures. larger output capacitor values (10f max) help to reduce no is e and improve load transient-response, stability and power-supply rejection. 9.7.3 input capacitor if the as1376 is used stand alone, an input capacitor at v in is required for stability. it is recommended that a 1.0f capacitor be connected between the as1376 power supply input pin v in and ground (capacitance value may be increased without limit). this capacitor must be located at a distance of not more than 1cm from the v in pin and returned to a clean analog ground. any good quality ceramic, tantalum, or film capacitor may be used at the input. a capacitor at v bias is not required if the distance to the supply does not exceed 5cm. if the as1376 device is used in the typical application as post regulator after a dc-dc regulator, no input capacitors are requ ired at all as the capacitors of the dc-dc regulator (c in and c out ) are sufficient if both components are mounted close to each other and a proper gnd plane is used. if the distance between the output capacitor of the dc-dc regulator and the v in pin of the as1376 is larger than 5cm, a capacitor at v in is recommended. 9.7.4 noise the regulator output is a dc voltage with noise superimposed on the output. the noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. noise is a random fluctuation and if not minimized in some app lications, will produce system problems. 9.7.5 transient response the series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be correc ted by the error loop. this ?propagation time? is related to the bandwidth of the error loop. the initial response to an output transient comes from the output capacitance, and during this time, esr is the dominant mechanism causing voltage transients at the output. more generally: units are volts, amps, ohms. (eq 15) thus an initial +50ma change of output current will produce a -12mv transient when the esr=240m ? . remember to keep the esr within s tability recommendations when reducing esr by adding multiple parallel output capacitors. after the initial esr transient, there follows a voltage droop during the time that the ldo feedback loop takes to respond to t he outp ut change. this drift is approx. linear in time and sums with the esr contribution to make a total transient variation at the output of: units are volts, seconds, farads, ohms. (eq 16) where: ? c load is output capacitor ? t = propagation delay of the ldo 20 log ? v out ? v in --------------- - ? ? v transient ? i output r esr ? = ? v transient ? i output = r esr t c load --------------- - + ?? ?? ? ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 15 - 19 as1376 datasheet this shows why it is convenient to increase the output capacitor value for a better support for fast load changes. of course th e formula holds for t < ?propagation time?, so that a faster ldo needs a smaller cap at the load to achieve a similar transient response. for insta nce 50ma load current step produces 50mv output drop if the ldo response is 1usec and the load cap is 1f. there is also a steady state error caused by the finite output impedance of the regulator. this is derived from the load regula tion spe cification discussed above. 9.7.6 exit from shutdown delay this specification defines the time taken for the ldo to awake from shutdown. the time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. it assumes that the voltage at v in is stable and within the regulator min and max limits. shutdown reduces the quiescent current to very low, mostly leakage values (<1a). 9.7.7 thermal protection to prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is bui lt into the device. die temperature is measured, and when a 150oc threshold is reached, the device enters shutdown. when the die cools sufficiently , the device will restart (assuming input voltage exists and the device is enabled). hysteresis of 25oc prevents low frequency oscillation b etween start-up and shutdown around the temperature threshold. 9.7.8 power supply sequencing the as1376 requires two different supply voltages active at the same time for correct operation. they are as given below. 1. v in , the power input voltage, that is regulated to provide the fixed output voltage. 2. v bias , the bias input voltage, supplies internal circuitry. it's important that v in does not exceed v bias at any time. if the device is used in the typical post regulation application as shown in figure 1 , the sequencing of the two power supplies is not an issue as v bias supplies both, the dc-dc regulator and the as1376. the output voltage of the dc-dc regulator will take some time to rise up and supply v in of as1376. in this application v in will always ramp up more slowly than v bias . in case v in is shorted to v bias , the voltages at the two supply pins will ramp up simultaneously causing no problem. only in applications with two independent supplies connected to the as1376 special care must be taken to guarantee that v in is always = v bias . 9.7.9 auto-discharge when the as1376 is placed in shutdown, a 100 ? path to ground is connected at the output. this path speeds up the discharge of the c apacitor(s) connected to the regulator output. assuming that v in remains constant and always >v out , output discharge time is calculated from the following relationship: (eq 17) where: ? t = specified time after regulator shutdown (sec) ? v reg = regulated output voltage (initial condition) ? r = 100 ? (typ) discharge resistance ? c = output capacitance (farad) in other words, the output discharge will reach 90% below the regulated output voltage in 2.2rc seconds; r and c defined as abo ve. vt ?? v reg e t rc ------- - ? = ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 16 - 19 as1376 datasheet - package drawings and markings 10 package drawin gs and markings the device is available in a 8-pin 2x2mm tdfn package. figure 22. drawings and dimensions no tes: 1. dimensions and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. 3. coplanarity applies to the exposed heat slug as well as the terminal. 4. radius on terminal is optional. 5. n is the total number of terminals. xxx abt symbol min nom max a 0.51 0.55 0.60 a1 0.00 0.02 0.05 a3 0.15 ref l 0.225 0.325 0.425 b 0.18 0.25 0.30 d 2.00 bsc e 2.00 bsc e 0.50 bsc d2 1.45 1.60 1.70 e2 0.75 0.90 1.00 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n8 ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 17 - 19 as1376 datasheet - package drawings and markings revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.2 initial revision 1.3 12 oct, 2011 afe changes made across document for version 1.3 1.4 12 dec, 2011 updated equations in power dissipation section ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 18 - 19 as1376 datasheet - ordering information 11 ordering information the device is available as the standard products listed in table 4 . non-standard devices from 0.5v to 1.1v are av ailable in 50mv steps and from 1.1v and 2.2v in 100mv steps. for more information and inquiries contact http://www.austriamicr osystems.co m/contact note: all products are rohs compliant. ? buy our products or get free samples online at icdirect: http://www.austriamicr osystems.co m/icdirect ? ? technical support is available at http://www.austriamicrosystems.com/technical-support ? ? for further information and requests, please contact us mailto: sales@austriamicrosystems.com ? or find your local distributor at http://www.austriamicros ystems.co m/distributor table 4. ordering information ordering code marking output description delivery form package as1376-btdt-ad 1 1. available on request abl adj 1a, l ow input voltage, low quiescent current ldo tape and reel 8-pin 2x2mm tdfn as1376-btdt-08 1 abm 0.8v 1a, low input voltage, low quiescent current ldo tape and reel 8-pin 2x2mm tdfn as1376-btdt-10 1 abn 1.0v 1a, low input voltage, low quiescent current ldo tape and reel 8-pin 2x2mm tdfn as1376-btdt-12 abt 1.2v 1a, l ow input voltage, low quiescent current ldo tape and reel 8-pin 2x2mm tdfn AS1376-BTDT-20 1 abp 2.0v 1a, low input voltage, low quiescent current ldo tape and reel 8-pin 2x2mm tdfn as1376-btdt-22 1 abq 2.2v 1a, low input voltage, low quiescent current ldo tape and reel 8-pin 2x2mm tdfn ams ag technical content still valid
www.austriamicrosystems.com/lods/as1376 revision 1.4 19 - 19 as1376 datasheet - ordering information copyrights copyright ? 1997-2011, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. ? contact information headquarters austriamicrosystems ag ? tobelbaderstrasse 30 ? a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 ? fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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